Asymmetrical devices for short gate length performance with disposable sidewall

ABSTRACT

An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high V T  net dopant adjacent to the source region and a relatively low V T  net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net V T  implant is provided in the central region of the channel and a relatively high net V T  implant is provided in the channel regions adjacent to the source and drain regions.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a field effect transistor (FET) with animplant within the gate length of the FET and a method of making theFET.

[0003] 2. Brief Description of the Prior Art

[0004] It has been found that there are advantages for an FET to have animplant in the channel region that does not extend from the source tothe drain and is aligned to the gate edge. For example, a pocket implantcan be used to reduce short channel length effects. Yet, it can beundesirable to have a pocket implant extend into the source/drain (S/D)area because of resulting increased junction capacitance. It has alsobeen found that there are advantages for an FET to have a region ofcontrolling V_(T) on the source side of the channel with a moreconductive V_(T) on the drain side. The short effective channel lengthand low source resistance of such an FET results in increased drivecurrent and the reduced influence of the drain provides superior shortchannel characteristics. In the prior art, angled implants and lateraldiffusions have been used to obtain channel impurity profilesself-aligned to the gate edge. However, these approaches havedisadvantages resulting from restrictions in the channel implantprofiles that can be obtained and from the interdependence of thechannel profile and the S/D extension profiles. It is therefore apparentthat transistors having an independent channel implant region that isself aligned to the S/D edge is highly desirable.

SUMMARY OF THE INVENTION

[0005] In accordance with the present invention, there is provided atechnique for fabrication of FET devices having a well controlledimplant region between the two source/drain regions, self aligned to theS/D edge as well as the FET itself. In one embodiment, this implantregion is used to create a controlling V_(T) region of shorter effectivelength than the S/D spacing. Preferably, the controlling V_(T) region ison the source side of the space between source and drain. In a secondembodiment, the implant region is a pocket implant with limitedextension into the S/D region. In a third embodiment, the implant is aS/D extension implant with extension into the channel region beingindependent of the diffusion of the S/D implant. The term “controllingVT region” as used herein refers to that region which is the leastconducting region and thus controls the current flow. For an n-channeltransistor, this will generally be the more positive (higher) V_(T). Thecontrolling region could have a positive V_(T) and the rest of thechannel could have a negative V_(T), or the controlling region couldhave a negative VT with the rest of the channel having a more negativeV_(T). The same applies for p-channel transistors except for a polarityreversal.

[0006] In accordance with the present invention, there is provided afabrication technique for fabrication of FET devices having a wellcontrolled sub-lithographic effective gate length, independent of gateorientation. The shorter effective channel length provides increaseddrive current since drive current is inversely proportional to channellength. The shorter effective channel length is achieved withoutrequiring that the physical gate also be as short as the effectivechannel length. This provides superior short gate length devicecharacteristics and avoids the problems inherent in requiring theshorter gate length during fabrication of the device.

[0007] One way to achieve the effective short channel is to use adisposable gate process with masked/disposable sidewalls. This isaccomplished by providing a doped substrate having spaced apartsource/drain regions with a pad oxide and a patterned mask over thesource/drain regions, preferably of silicon nitride, leaving the gateregion exposed after disposal of the disposable gate. A removablesidewall is formed on the mask, preferably with silicon nitride, and theremaining gate region between the disposable sidewalls is filled withsilicon dioxide with the surface then being planarized, preferably witha chemical mechanical polish (CMP). The sidewall adjacent to the sourceregion is then removed by depositing and patterning a resist over theplanarized surface and etching. A high V_(T) implant is then performedthrough the space from which the sidewall was removed to dope thechannel region adjacent to the source region. The remaining sidewall isthen removed. This is followed by a low V_(T) implant in the channelregion between the source and drain regions. It should be understoodthat the high V_(T) implant can be a counter doping of the low V_(T)implant with appropriate masking to perform the implants in this manner.The result is an effective channel length, L, which is independent ofthe original disposable gate length. Fabrication then proceeds instandard manner to complete the device.

[0008] As a second embodiment, the low V_(T) channel implant can beperformed initially after removal of the disposable gate and formationof disposable sidewalls on the mask as in the first embodiment, thesidewall on the source side is retained and the sidewall on the drainside is removed with appropriate deposition and patterning of resist andetching. A low V_(T) is then provided into the exposed portion of thechannel. The remaining sidewall at the source end of the channel is thenremoved and a high V_(T) implant is then provided of oppositeconductivity type to the low V_(T) implant to provide the same result asin the first embodiment. Fabrication then proceeds in standard manner tocomplete the device.

[0009] As a third embodiment, it is desirable to add a liner over themask surface, sidewalls and pad oxide prior to fabrication as notedabove with reference to the first and second embodiments. The liner ispreferably silicon nitride. The liner aids etch selectivity and protectsthe surface of the silicon when performing the implants.

[0010] As a fourth embodiment, the FET can be made symmetrical ratherthan asymmetrical as described in the first and second embodiments witha different implant in the center of the channel region relative to thesource and drain ends of the channel region. An implant can be performedfollowing sidewall formation. The sidewalls would then be removed andthe entire channel region would be doped n- or p-type to provide eithera less heavily net doped region adjacent the source and drain regions ifthe same conductivity type dopant is used or a more heavily net dopedregion adjacent the source and drain if the opposite conductivity typedopant is used. The resist pattern used to mask removal of selectedsidewalls can also distinguish n- and p-channel transistors fordifferent V_(T) implants. Optionally, an implant can be performed beforeformation of the sidewalls, followed by an implant after formation ofthe sidewalls. For this option, the sidewall can be left in place forformation of the actual gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIGS. 1A to 1D represent a process flow for formation of anasymmetrical FET device for short gate length performance in accordancewith a first embodiment of the present invention;

[0012]FIGS. 2A to 2C represent a process flow for formation of anasymmetrical FET device for short gate length performance in accordancewith a second embodiment of the present invention;

[0013]FIG. 3 shows a step in the process flow in accordance with a thirdembodiment of the present invention;

[0014]FIGS. 4A and 4B show a process flow for formation of a symmetricalFET device for short gate length performance in accordance with a fourthembodiment of the present invention;

[0015]FIGS. 5A to 5C show a process flow for formation of an FET inaccordance with a fifth embodiment of the present invention; and

[0016]FIGS. 6A and 6B show a process flow for formation of an FET inaccordance with a sixth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] In accordance with a first embodiment of the invention, theeffective short channel is achieved by using a disposable gate processwith masked/disposable sidewalls as shown in FIGS. 1A to 1D. For ann-channel device (it is understood that all conductivity types will beopposite for a p-channel device), there is provided a p-doped substrate1 having spaced apart source/drain regions 3, 5 with a pad oxide 7 overthe substrate and a patterned silicon nitride mask 9 over thesource/drain regions. This arrangement is provided, leaving the gateregion exposed after prior disposal of the disposable gate in standardmanner as shown in FIG. 1A. A removable polysilicon sidewall 11, 13 isformed on each side of the nitride mask 9 and the remaining gate regionbetween the disposable sidewalls is filled with silicon dioxide 15 withthe surface then being planarized, preferably with a chemical mechanicalpolish (CMP) as shown if FIG. 1B. The sidewall 11 adjacent what willultimately be the source region is then removed by depositing andpatterning a resist over the planarized surface and etching in standardmanner. A high V_(T) implant is then performed through the space fromwhich the sidewall was removed to dope the channel region 17 adjacent tothe source region 3 as shown in FIG. 1C and the silicon dioxide 15 andremaining sidewall 13 are then removed. This is followed by a low V_(T)implant in the channel region between the source and drain regions toleave the high V_(T) region 17 adjacent to the source region 3 and a lowV_(T) region 19 adjacent to the drain region 5 as shown in FIG. 1D.Optionally, the low V_(T) implant can be performed before formation ofthe sidewalls.

[0018] It should be understood that the V_(T) of region 17 is a resultof the combination of what has been referred to as the high V_(T) andthe low T implant. One can be a counter-doping of the other. The resultis an effective channel length, L, which is independent of the originaldisposable gate length. Fabrication then proceeds in standard manner tocomplete the device.

[0019] As a second embodiment, the low V_(T) channel implant can beperformed prior to the high V_(T) implant. After removal of thedisposable gate, disposable sidewalls are formed on the mask as in FIG.1B of the first embodiment and as shown in FIG. 2A wherein likereference characters refer to the same or similar structure. Thesidewall on the source region side 11 is retained and the sidewall onthe drain region side 13 is removed with appropriate deposition andpatterning of resist and etching in standard manner. A low V_(T) implantis then provided into the exposed portion 21 of the channel as shown inFIG. 2B. The remaining sidewall 11 at the source end of the channel isthen removed and a high V_(T) implant is implanted into the channelregion between the source and drain regions. Preferably, the high V_(T)implant is of opposite conductivity type to the low V_(T) implant toprovide a high V_(T) region 23 and a low V_(T) region 21. Fabricationthen proceeds in standard manner to complete the device. Optionally, thehigh V_(T) implant can be performed prior to formation of the sidewalls.

[0020] As a third embodiment, it is desirable to add a liner 25 over themask surface, sidewalls and pad oxide prior to fabrication as notedabove with reference to the first and/or second embodiments andparticularly over the structure as shown in FIG. 1A and the structure asshown in FIG. 2A prior to formation of the sidewalls 11, 13 withsubsequent formation of the sidewalls 11, 13 over the liner as shown inFIG. 3. The liner 25 is preferably silicon nitride. Fabrication thenproceeds as in the prior embodiments as discussed above.

[0021] As a fourth embodiment as shown if FIGS. 4A and 4B, the FET canbe made in a symmetrical rather than asymmetrical embodiment asdescribed in the first and second embodiments with a different implant27 in the center of the channel region as shown in FIG. 4A. Optionally,implant 27 may include a punch-through implant. The sidewalls 11, 13 arethen removed and the entire channel region is doped wither n- or p-typeto provide either a less heavily net doped region adjacent the sourceand drain regions 29 if the same conductivity type dopant is used or amore heavily net doped region adjacent the source and drain regions ifthe opposite conductivity type dopant is used and the oppositecharacteristic in region 27 as shown in FIG. 4B. Optionally, the implantin the full channel region can be performed prior to sidewall formation.Fabrication then proceeds in standard manner to complete the device.

[0022] As a fifth embodiment as shown in FIGS. 5A to 5C, the FET can bemade symmetrical with the implant in the channel regions adjacent to thesource and drain being performed prior to the implant in the centralregion. As in the first embodiment, sidewalls 11 and 13 are formed andthe central region 15 is filled and planarized as shown in FIG. 5A.Sidewalls 11 and 13 are then removed and an implant is performed intoregions 50. As depicted in FIG. 5B, the implant regions 50 may be pocketimplants. Optionally, source/drain extension or V_(T) adjust implantscan be performed at this time. Center masking material 15 is thenremoved and in implant is performed into the channel region 52 betweenthe source and drain regions.

[0023] As a sixth embodiment, the sidewalls are left in place, reducingthe physical gate length, as shown in FIGS. 6A and 6B. An implant isperformed in the full channel region 60 prior to formation of thesidewalls. A second implant is performed into region 64 after formationof the sidewalls, resulting in a different implant profile in regions 62versus region 64. Sidewalls 11 and 13 can then be left in place asformation of the gate proceeds in normal fashion. Optionally, sidewall11 or sidewall 13 can be removed with appropriate pattern and etch stepsprior to or subsequent to the implant to region 64.

[0024] Optionally, the sidewall material can be of the same material asthe masking material and left in place or removed with a timed isotropicetch prior to gate formation.

[0025] Though the invention has been described with reference tospecific preferred embodiments thereof, many variations andmodifications will immediately become apparent to those skilled in theart. For example, the opening for the damascene gate can be made by atrench etch into the masking material rather than by removal of adisposable gate. Various materials or stacks of materials can be usedfor the masking material, the sidewalls, and the fill material. Thesource/drain implants can be performed after the actual gate formationrather than with the disposable gate, and the edge of the source/drainimplant relative to the opening for the damascene gate can vary fromthat shown, and a source/drain extension may be used. The implants intothe various regions encompassed by the gate opening can include but arenot restricted to threshold adjustment implants, source/drain extensionimplants, pocket implants and punch through implants. Multiple implantsof different species or energy can be performed in any of the regions toobtain the desired doping profile. The depth of implants illustrated isnot intended to be restrictive. Different sequences of sidewallformation, sidewall removal, and implantation, including multiplesidewall formation can be used. Sidewalls can be added after completionof the channel region implants to adjust the physical gate length. It istherefore the intention that the appended claims be interpreted asbroadly as possible in view of the prior art to include all suchvariations and modification.

1. A method of fabricating a transistor which comprises the steps of:(a) providing a semiconductor substrate having a first source/drainregion and a second source/drain region therein; and (b) providing achannel region between said first and second source/drain regions insaid substrate having a first dopant profile in a first regionsubstantially in said channel region and a second dopant profiledifferent from said first dopant profile in a second regionsubstantially between the first region and said first source/drainregion, the second dopant profile comprising an implant substantiallybounded between said first region and said first source/drain region. 2.The method of claim 1 wherein said channel region is formed byimplanting a dopant providing a relatively high V_(T) dopant profileadjacent to said first source/drain region and implanting a dopantproviding a relatively low dopant profile adjacent to said secondsource/drain region.
 3. The method of claim 1 wherein said channelregion is formed by implanting a dopant providing a relatively low V_(T)dopant profile along said channel and then selectively implanting adopant providing a relatively high V_(T) dopant profile adjacent to saidfirst source/drain region.
 4. The method of claim 2 wherein said channelregion is formed by implanting a dopant providing a relatively highV_(T) dopant profile adjacent to said first source/drain region andimplanting a dopant providing a relatively low dopant profile adjacentto said second source/drain region.
 5. The method of claim 2 whereinsaid channel region is formed by implanting a dopant along the entirechannel and then selectively implanting a dopant providing a relativelyhigh V_(T) dopant profile of opposite conductivity type only adjacent tosaid first source/drain region to provide a net relatively high V_(T)region only adjacent to said first source/drain region
 6. A method offabricating a transistor which comprises the steps of: (a) providing asemiconductor substrate having source and drain regions therein; and (b)providing a channel region between said source and drain regions in saidsubstrate having a dopant providing a relatively low V_(T) dopantprofile central region between said source and drain regions and regionsin said channel region between said source region and said centralregion and between said drain region and said central region having adopant providing a relatively high V_(T) dopant profile.
 7. The methodof claim 6 wherein said channel region is formed by implanting a dopanthaving a relatively low V_(T) dopant profile intermediate said sourceand drain regions and implanting a dopant having a relatively high V_(T)dopant profile adjacent to said source and drain regions.
 8. The methodof claim 6 wherein said channel region is formed by implanting a dopanthaving a relatively low V_(T) dopant profile along said channel and thenselectively implanting a dopant having a relatively high V_(T) dopantprofile adjacent to said source region.
 9. A transistor which comprises:(a) a semiconductor substrate having source and drain regions therein;and (b) a channel region between said source and drain regions in saidsubstrate having a relatively low V_(T) central region between saidsource and drain regions and relatively high V_(T) regions adjacent tosaid source and drain regions.
 10. The transistor of claim 9 whereinsaid channel region is an implanted low VT dopant intermediate saidsource and drain regions are an implanted high V_(T) dopant adjacentsaid source and drain regions.
 11. The transistor of claim 9 whereinsaid channel region is an implanted relatively low V_(T) dopant alongsaid channel and a selectively implanted relatively high V_(T) dopantadjacent to said source region.
 12. A method of fabricating a transistorwhich comprises the steps of: (a) providing a substrate; (b) providing afirst mask layer over said substrate, said first layer having a trenchextending therethrough to said substrate; (c) forming sidewalls in saidtrench with a material different from said first mask layer; and (d)performing an implant into said substrate through said trench, saidlayer providing a mask to said implant external of said trench.
 13. Themethod of claim 12 further including the step of removing a portion ofsaid sidewall prior to performing said implant.
 14. A method offabricating a transistor which comprises the steps of: (a) providing asubstrate; (b) providing a first mask layer over said substrate, saidfirst layer having a trench extending therethrough to said substrate;(c) forming sidewalls on said trench with a sidewall material differentfrom said first mask layer; (d) filling the space bordered by saidsidewalls with a filling material different from said sidewall material;(e) removing at least a portion of said sidewalls while retaining atleast a portion of said filling material; and (f) performing an implantinto said substrate through said trench, said layer, said fillingmaterial and any remaining sidewall providing a mask to said implantexternal of said trench.
 15. A transistor which comprises: (a) asemiconductor substrate having a first source/drain region and a secondsource/drain region therein; (b) a channel region between said first andsecond source/drain regions; (c) a gate dielectric disposed outwardlyfrom said channel region; (d) a gate electrode disposed outwardly fromsaid gate dielectric; and (e) a dopant in said substrate comprising animplant aligned with said gate contained substantially within aprojection of said gate electrode to said substrate, the projection ofthe area of the implant to the surface of the substrate being less thanthe projection of the gate.
 16. A method of fabricating a transistorwhich comprises the steps of: (a) providing a substrate; (b) providing afirst layer of said substrate, said first layer having a trench forformation of a gate; (c) forming a sidewall within said trench; and (d)performing a first implant into said substrate, said first implant beingpartially masked by said sidewall.
 17. The method of claim 16 wherein aportion of said sidewall is removed prior to said first implant.
 18. Themethod of claim 16 further including performing a second implant intosaid substrate which is not masked by said sidewall.
 19. The method ofclaim 18 wherein said second implant is performed prior to formation ofsaid sidewall.
 20. The method of claim 18 wherein said second implant isperformed after removal of said sidewall.
 21. The method of claim 16further including the steps of: (e) filling any space adjacent saidsidewall; (f) planarizing the surface of the structure being fabricated;and (g) removing a portion of said sidewall.
 22. The transistor of claim15 wherein one edge of said implant region is substantially aligned withone edge of said gate electrode and the opposite edge of said implantregion is within the projection of the gate electrode.
 23. A transistorwhich includes: (a) a substrate; (b) a gate electrode disposed over saidsubstrate; and (c) a punch through implant in said substrate containedwithin a projection of said gate electrode.